A video RAM (VRAM) is a dynamic random access memory (DRAM) having a serial input/output (I/O) port coupled to a serial access memory (SAM). The SAM permits a block of stored data to be rapidly accessed, while the normal access function of the DRAM is also occurring. The information stored in the SAM is normally obtained from, or input into, a primary memory on the VRAM. The primary memory is typically configured as a DRAM array and is accessed according to normal DRAM protocols.
Information can be written into the VRAM at DRAM address speeds and output through the serial access port, or vice versa. This serial writing and access capability is convenient for video applications because some address sequences, such as pixels in a raster scan, are predetermined.
The McLaury U.S. Pat. No. 5,325,502 entitled PIPELINED SAM REGISTER SERIAL OUTPUT, is commonly assigned to Micron Technology, Inc., the assignee of the present application, and is incorporated herein by reference. The U.S. Pat. No. 5,325,502 patent describes a VRAM having a faster serial read operation by pipelining the serial read operation. The pipelined serial read operation performs many of the necessary serial read operations steps concurrently, rather than performing all of the steps serially as was done previously. In particular, the preferred embodiment described in the U.S. Pat. No. 5,325,502 patent pipelines the serial read operation by partitioning the serial read operation to form a sensing operation, a counter operation, and an output operation wherein all three operations proceed concurrently.
The U.S. Pat. No. 5,325,502 patent describes a pipelined SAM architecture, but does not address the situation where a split read transfer operation is performed on a SAM split boundary. A need exists for a pipelined SAM architecture V/RAM, such as described in the U.S. Pat. No. 5,325,502 patent, which performs a split read transfer operation which meets normal, non-pipelined SAM specifications.